Current and future state-of-the-art integrated circuit (IC) manufacturing technologies demand the capability to fabricate features with a pitch below 60 nm. Currently developed photolithography tools, however, are limited to patterning a single pitch not less than 80 nm. A key to future-generation lithography for IC manufacturing is to inexpensively deploy tools and enable processes to efficiently pattern smaller features with smaller pitches. Several solutions have been proposed for manufacturing ICs below 60 nm.
One solution is extreme ultraviolet (EUV) lithography that utilizes a 13.5 nm wavelength light source for use in 20 nm technology nodes and beyond (e.g., 14 nm). However, EUV lithography is difficult to implement because it requires a stable and powerful light source of EUV light. Thus, wafer throughput is very low compared to current standards. Further, because all matter absorbs EUV light, reflective lenses (e.g., mirrors) must be used in design tools instead of refractive lenses. This imposes an extremely restricted requirement on the flatness of the mirrors, which poses a large technical challenge. The absorption of EUV light by all matter also demands a high vacuum environment and an ultra-clean manufacturing practice throughout the entire supply chain, which significantly increases cost.
Another solution involving spacer or sidewall technology is based on currently employed optical lithography and uses a series of deposition and etching processes to convert a mandrel structure into two separated structures on the sides. Hence, the solution allows for doubling the density and splitting the pitch of features by a factor of two. However, the extra deposition and etching increases the complexity of the process and the manufacturing cost and is still difficult to extend to even smaller size features.
Another solution is double patterning technology that involves multiple optical lithography processes to double the density of features. However, similar to the second solution above, the double patterning increases the cost for the extra processing steps and has challenges concerning mask overlay issues.
Another solution is directed self-assembly (DSA) that uses the self-assembling capability of block copolymers (BCPs) to obtain periodic nano-features on a surface patterned with chemical functionalities or topographies, such as chemical epitaxy or graphoepitaxy, respectively. The BCP self-assembles to form micro-phase separated structures, where the relative length of the polymer chain for either block determines the morphology the material will adopt. With the desired morphology and orientation, the patterns formed by the BCPs can be transferred onto a substrate (e.g., a layer associated with the production of a semiconductor device) through several steps associated with BCP lithography. Structures can be formed using the BCP, such as cylinders or lamellae, which can then be transferred through reactive ion etching to a substrate. For graphoepitaxy, a neutral surface in combination with topographical features controls the location and orientation of the BCP microdomains. For chemical epitaxy, a neutral surface in combination with chemical pinning regions controls the location and orientation of the BCP microdomains. After application of the BCPs to the topographically or chemically patterned surfaces, thermal or solvent annealing methods separate the BCPs into the microdomains.
DSA is based on current state-of-the-art 193 nm immersion lithography with a few additional processing steps that are compatible with current manufacturing flows. Every DSA-associated processing step can be implemented within one to several minutes allowing for throughput to be analogous to current 193 nm lithography flow. However, although individual process steps have been shown using DSA-implemented technologies, it has not been shown how DSA structures can be designed to print a layout of complementary metal-oxide semiconductor (CMOS) standard transistor cells, or how exactly a layout should be designed to enable DSA.
A need therefore exists for methodology enabling fabrication of a DSA standard cell design and the resulting cell design.